The Design of Class 1 MVB Device Controller Based FPGA
|School||Dalian University of Technology|
|Course||Communication and Information System|
|Keywords||Train Communication Network MVB Class 1 MVB Controller FPGA|
Train Communication Network (TCN) which bases on distributed control system is divided into Wire Train Bus (WTB) which is used for interconnecting vehicles in Open Trains and Mutifunction Vehicle Bus (MVB) which is used for connecting fixed devices in a vehicle. Referred to the products of MVB, the MVB controller which realizes the protocol of link level is the key technology of MVB. Its function is to realize the communication between MVB and the linked physical device. The MVB related technologies and products are monopolized by some foreign companies, which baffles the applications of MVB in our country. This situation doesn’t profit the research of our own products and the establishment of our own standard.For all of the reasons above, MVB is researched and on the base of understanding the MVB communication mechanism, a method with FPGA to replace the MVB controller ASIC is proposed in this paper. Devices attached to the MVB are divided into five classes according to the TCN protocol. Class 1 devices which are most widely used in TCN can realize automatic communication without the help of CPU. The purpose of this paper is to design Class 1 MVB Controller with FPGA.Based on the function of the class 1 MVB controller to realize, a top-down module design method is adopted and the design is divided into three modules: encoder, decoder and class 1 device controller. To realize the functions of encoder, this paper divides it into following basic units: bit control, CRC generator, FIFO and Manchester coding etc. The decoder is also divided into start detecting, clock recover, frame delimiter detecting, data decode, CRC checkout, decoding control and length error detecting units etc. And class 1 device controller module is divided into error handle, master frame register, MCU and traffic memory controller units etc. The RTL design of all the modules above is completed with Verilog HDL.After the RTL design, the function simulation platform for the whole system is constructed and the design is validated on it. Then, the design is synthesized and timing simulated with ISE for XC2S200 FPGA. The functions of the MVB controller such as encoder, decoder and class 1 device controller are validated and frame waveforms in complete conformance with IEC61375-1 protocol are achieved.