Sigma-Delta ADC decimation filter in Research and Implementation
|Course||Microelectronics and Solid State Electronics|
|Keywords||S-ΔA / D converter Oversampling SNR Compensation filter CSD code|
The contents of this article Sigma-Delta ADC digital decimation filter in research and design. The study design Sigma-Delta converter (sampling frequency 44.1KHz) mainly used in consumer digital audio receivers, digital audio recorders, including portable CD-R (Compact Disc Recordable), DCC (Digital Content Creation) , MD (MiniDisc), DAT (Digital Audio Tape), multimedia consumer electronic devices and music sampling synthesizer. So the research applied to the audio system of the ADC chip has great practical significance. Decimation filter is a Sigma-Delta analog to digital converter is an important component. Low word, high sampling frequency, the digital modulation signal is converted into a high word rate, the Nyquist frequency sampled signal. This paper designs and implements an oversampling rate of 256 digital decimation filter is applied 2-1 cascaded third-order ΔΣ modulator. The decimation filter comprises: cascaded integrator-comb (CIC: Cascaded-Integrated-Comb) filter, compensating filters and two narrow-band finite impulse response half-band filter. Apply the principles of a comb filter replacement saves chip area and power consumption. Compensation filter to achieve a down-sampling and frequency compensation two functions, reducing the hardware overhead. On the basis of the prior art, the use of half-band filter impulse response symmetry, to improve the rate of the filter, power consumption, performance, and more importantly, reduce the chip area. Filter coefficients are used CSD (Canonic Signed Digit) code implementation. Compensation and half-band filters are used such as corrugated design methods, the design uses a multistage multirate signal processing circuit. Circuit design parameters are as follows: a digital voltage of 1.8V, the dynamic range of 98dB, noise and harmonic distortion ratio 96dB, median 18 valid signal, the decimation filter passband ripple 0.006 dB, stop-band attenuation of 110dB, four linear phase decimation filter, 256-fold lower sampling rate. The whole design through the MATLAB system simulation, Verilog HDL RTL-level coding, Modelsim SE RTL level code before the gate-level simulation and code simulation, Synopsys Design Compiler comprehensive, Encounter layout, Calibre DRC and LVS. After the entire filter FPGA verification, using SMIC Shanghai Co., Ltd. 0.18um CMOS mixed signal process flow sheet and tested, the test results basically meet the design requirements.