Study on Ethernet MAC Protocol and Its FPGA Implementation
|Course||Microelectronics and Solid State Electronics|
|Keywords||Ethernet MAC Embedded System VerilogHDL FPGA|
At present, the Ethernet IEEE802.3 protocol and TCP/IP protocol are the first choice for embedded system to access the internet. The core of the Ethernet protocol is the transmission channel is shared by multi-nodes, and the information collision is solved by CSMA/CD (carrier sense multiple access/collision detection) to control the channel.Ethernet IEEE802.3 protocol is mainly studied in this dissertation. The embedded Ethernet MAC controller is designed based on FPGA. The 10/100Mbps Ethernet controller is designed with Verilog-HDL, which includes bus interface, Tx/Rx modules, flow control module, etc. And the parallel CRC32 algorithm, HASH algorithm, random number algorithm based on Cellular Automata and LSFR of relative components are illustrated. The Ethernet MAC controller supports the 10/100Mbps dual speeds, the half duplex/duplex transition modes, and communicates with PHY layer though MII interface.To reduce the power consumption, the clock management module is designed. The clock is distributed with respect to the Ethernet MAC controller’s working condition, so it can be applied in the environment of low power necessity.The complete function verification environment and test vectors are constructed. The verification method of Fault-injection technology is discussed based on System Verilog language. The designed Ethernet controller is implemented in Altera FPGA. The results of logic simulation and FPGA physical verification of board level indicate that the related functions of the Ethernet MAC controller are realized.