Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Data communication > Data transmission technology

Design of De-mapper and Viterbi Decoder in COFDM System

Author YuXi
Tutor ChenYongEn
School Tongji University
Course Signal and Information Processing
Keywords Coded orthogonal frequency division multiplexing Viterbi algorithm Demapping Plus selection
CLC TN919.3
Type Master's thesis
Year 2007
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Coded orthogonal frequency division multiplexing (COFDM, Coded Orthogonal Frequency DivisionMultiplexing) is a widely used high-speed wireless communications technology , especially for frequency-selective channel . In this paper, the terrestrial digital broadcasting ( DVB - T ) receiver chip , for example , the the COFDM system demapping and Viterbi decoder module design . The Viterbi decoding algorithm is a maximum likelihood algorithm , it is based on sequence information of the receiver , the search for the best path having the smallest path metric in the trellis diagram , mainly generated by the branch metric unit ( BMGU BranchMetric Generate Unit ) , the path metric profile unit (PMUU, Path Metric Update Unit) and the survivor path management unit ( SMU the Survivor management unit ) is composed of three parts . With increasing constraint length Viterbi decoder complexity increases rapidly , in order to trade-off speed of the chip area and power consumption , the design of the standard Viterbi algorithm has been modified , a Viterbi decoder has the following characteristics : 1.4 bit soft input. 2 . Decoding speed greater than 32 Mbit / s , the decoding throughput of 2 bits / clock . 3.32 than the election plus ( CSA , Compare - Select -Add ) unit . 4 . Lookahead structural design than the election plus adder unit . 5. Improved design for parallel adaptive Viterbi algorithm . 6. Ahead backtracking algorithm and can be configured to back depth . Design a simplified solution mapping algorithm , using 4-bit soft-output support QPSK, 16 - QAM and 64-QAM constellation mapping mode . At the same time considering the channel state information ( CSI ChannelStatus Information ) demapper for flat fading channel and frequency selective fading channel . The channel fading speed configuration of two CSI calculation algorithm . In order to evaluate and verify the performance of the algorithm , create a floating-point C and the fixed-point C model . The entire design on the VCS functional simulation in the Nios II development board functional test DesignCompiler comprehensive PrimeTime static timing analysis .

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