Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Radio equipment,telecommunications equipment > The sending device,the transmitter > Other

Design of LVDS High Speed Transceiver

Author XieZhanQi
Tutor DaiQingYuan
School Shanghai Jiaotong University
Course Microelectronics and Solid State Electronics
Keywords LVDS transmitter receiver LDO bandgap reference analog adaptive equalizer
Type Master's thesis
Year 2008
Downloads 672
Quotes 18
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LVDS (Low Voltage Differential Signaling) is an international universal interface standard that applied to high speed signal transmission. It is helpful to solve the bottleneck in the extensive application fields because of its advantages such as high speed, low power dissipation, low noise and cost saving. With the rapid development of communication technology, the need for higher bit rate and longer distance transmission on cable becomes more and more urgent. Thus the realization of a Gbps and tens of meters transmission on cable becomes not only a technology barrier but also a research hotspot. Many companies such as NS and TI have done a lot of research in the field.Under such background, this project designs a LVDS transceiver with a 2 Gbps data rate and transmission distance of 10m. The objective is to realize a LVDS tranceiver chip that integrates PLL and bandgap.On the base of theoretical analysis, the LVDS driver and receiver are deeply studied. In the LVDS driver circuit design, a novel common mode feedback circuits is proposed to meet the differential mode output voltage compatible with LVDS standards. The bias circuit with bandgap voltage source structure has a high stability. A Low Dropout Regulator is designed to apply a pure and stable stabdard power supply. After a exploration of the principle and design method of equalizer,an analog adaptive equalizer circuit is introduced into the receiver to meliorate the capability of long-distance transmission. Then ESD protection design is studied, as it must be considered in high speed chip design. And at last the fail-safe issue, an important issue of LVDS, is analyzed.The CDR, PLL, DLL designs have been discussed by other members of this group and not been presented in this paper.The LVDS transceiver chip is designed in TSMC 0.25um, 3.3v, 1P5M process. The project is expected to be completed in one year.

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