Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer software > Program design,software engineering > Software Engineering > Software Development

The Design and Realization of TD-SCDMA Radio Repeater’s Software

Author ZhangYing
Tutor MengLiMin;HuaJingYu
School Zhejiang University of Technology
Course Communication and Information System
Keywords TD-SCDMA repeater pre-synchronization power ratio detection (PRD) FPGA
CLC TP311.52
Type Master's thesis
Year 2007
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3G industry will be rapid developed in 2007.At the beginning of 2007,the global 3G users have more than 150 million,with 100 million users use WCDMA and 50 million of CDMA2000 users.As China’s self-developed 3G wireless communication system TD-SCDMA has also accelerated the progress of its development,it has completed its outdoor coverage of the test,and will turn to indoor coverage test.At the same time,as the extension of base station, the repeater also needs to vigorously develop.But TD-SCDMA system is a clock’s synchronous system,it has stringent requirements with synchronization, and which set a higher demand to Repeater 3G.In TD-SCDMA system,SCDMA means synchronous CDMA;its terminal signal which transmits in uplink is completely synchronized in base station’s demodulator.To achieve synchronous CDMA,we must resolve the problem of synchronous detecting,establishing and maintaining in downlink.In synchronous CDMA system,the detecting of synchronization is completed by correlation function in software.Traditional correlation algorithm requires not only a long time and high power consumption,but the high complexity of in implementation.In this paper,Ⅰproposed a non-correlation algorithm Power Ratio Detect (PRD)to achieve TD-SCDMA system downlink pre-synchronized,with following correlation,it can realize the downlink synchronization fast and simply and test the correctness of the algorithm through Matlab simulation. Then through hardware description language Verilog HDL,it verifies the realization of its practical feasibility in FPGA.

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