Based FPGA reconfigurable chip on the system
|Course||Microelectronics and Solid State Electronics|
|Keywords||Dynamically Reconfigurable Partially reconfigurable Reconfigurable Computing Wavelet Transform Lifting Algorithm|
ASIC chip development costs of rapid growth, with the progress of the semiconductor manufacturing process, time-to-market requirements increasingly urgent, also proposed increasing user flexibility in product design requirements, leading ASIC chip design is increasingly difficult. In recent years, reconfigurable hardware showed significantly stronger than the ASIC development momentum due to the flexibility and cost advantages. But can be re-configured hardware inherent weaknesses such as high power consumption, slow, resource redundancy so that it still can not meet the requirements in the face of complex functional design, so people began to consider the technical integration of the ASIC with reconfigurable to find a middle road between the hardware - Programmable System on Chip SOPC. SOPC not only can reduce the risk of developing SOC chip, reducing time to market, and the the flexible reconfigurable ability to provide the same chip used in different applications, in particular, the constant change and development standards applicable to the product development, for example, communications and network chip products. The dynamically reconfigurable reconfigurable during system operation can be repeated configured to perform different functions at different times. Reconfigurable and static and dynamic reconfigurable can more fully take advantage of reconfigurable hardware. Dynamic reconfiguration technology research in international hot spots, especially in reconfigurable computing aspects. The technology already has made significant progress in theory, but there are still many deficiencies. The future development direction of the FPGA group is doing to support dynamic reconfiguration SOPC hardware. This is a huge project, the work done in this article is a part. This work consists of two parts: the first part is focused on the design of the General SOPC hardware platform; second part is for specific applications, dynamically reconfigurable hardware platform design. The innovation of this paper is as follows: 1. References of existing SOPC hardware platform, and to consider the requirements of dynamically reconfigurable propose a new SOPC hardware platform, the platform the CPU, nuclear multiple FPGAIP, on-chip memory, system interconnect , configuration of hardware such as FPGA IP core system by programmable interconnect resources connected to the on-chip memory. In order to support the design of the hardware platform, and further refined the problems and solutions. 2. Consider a reconfigurable hardware platform optimized for a specific application design. The applications selected as JPEG2000 and MPEG-4 compression standard wavelet transform static texture image. Proposed a reconfigurable 2D wavelet transform hardware platform, the overall structure of the water operation between data packets input, ranks transform without memory. The results show that the hardware platform is an efficient high-speed structure. 3 wavelet transform of the row direction in the way the input data packet, the operation of the different groups is serial in time, and the desired operation is different. The line direction wavelet transform dynamically reconfigurable thought hardware design with reconfigurable hardware the MUX switch while the system is running in order to achieve the different groups corresponding operation does not affect the speed at the same time save the area.