Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Information Theory

The Research on Some Capacity-Approaching Codes and Their VLSI Designs

Author LiuXiaoTong
Tutor ChenYongEn
School Tongji University
Course Control Theory and Control Engineering
Keywords low density parity check code Tanner graph girth density evolution theory message propagation algorithm turbo code maximum a posteriori algorithm linear-approximation algorithm base on minimal square error interleaver sliding window algorithm throughput
CLC TN911.2
Type PhD thesis
Year 2007
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With the invention of turbo codes and the rediscovery of low-density parity-check(LDPC) codes, iterative decoding techniques have been receiving more and more attentions. The idea of iterative techniques has been applied not only to coding/decoding, but also to synchronization, equalizer and channel estimation. An important aspect in the study of iterative decoding is the tradeoff between decoding performance and complexities. For both LDPC codes and turbo codes, optimum decoding algorithms can provide the best performance. However, complicated operations are involved in the optimum decoding, and prohibit the wide applications of LDPC codes and turbo codes in the next generation digital communication systems. Although in some literatures, there exist sub-optimum decoding algorithms for both LDPC codes and turbo codes, the decoding performance is degraded with the sub-optimum algorithms, and under some circumstances, the gap is very large.In this paper, we mainly investigate the improvement of decoding algorithms for both LDPC codes and turbo codes and their VLSI designs.For LDPC codes, we first summarize some existent coding and construction techniques. Then, some reduced complexity decoding algorithms(λ-min, BP-based, APP-based and APP algorithms) are compared with the original BP algorithm. As for the parameters in the improved algorithm, we find the optimum value ofβfor compensatedλ-min algorithm being 0.35 by simulations(The value 0.35 is fit for the LDPC codes in this paper. If the codes are different, the value will be changed). In the aspect of the VLSI design, we give a high efficient scalable decoder architecture for LDPC codes.This architecture adjusts the parallel processing factor M based on the serial frame to increase decode speed. The decoding complexities, memory requirements, throughput and parity-check matrix fit for this architecture are analyzed.For decoding turbo codes, some existent decoding algorithm, such as Max-Log-MAP algorithm, Log-MAP algorithm and SOVA algorithm, are reviewed. Then, the computational complexities and the difference between them are analyzed. After this, we present a new decoding algorithm called a linear-approximation decoding algorithm based on minimal square error(MSE). We analyze its computational complexities and give the simulation results. For some parameters including encoding constraint, iterative number, interleaver size, bit rate and decode algorithm having an influence on the decoding performance for turbo codes,we summarize the principle and method for designing turbo codes by simulations. For VLSI designs, we discuss the influence of the fixed-point, the main window and the guard window on decoding performance and analyze the memory requirements for real-time algorithms. Finally, The VLSI design for 3GPP turbo codes is done and the simulation results are gived.

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