The Verification of7816Interface Module Based on VMM

As the complexity of the rapid growth, validation will become the most challengeto integrated circuit in the development process. In fact, verification work account for60~80percent of total product development cycle. More and more of the project began touse validation methodology based on SystemVerilog to get more reuse scalability, morecomprehensive coverage of the function, and more reasonable the hierarchical structureof validation.This paper,based on the VMM (Verification Methodology Manual) validationmethodology to verify7816interface module of USB-key chip. Realize the modulelevel validation efficient, arrangement, reusable test platform. By analysis of the7816module function point, write a function coverage model, and the abnormal state of FIFOassertions validation.This paper has developed test case to simulate and verificate all thefunctions of7816module. All indexes of code coverage fulfill the requirements ofproject team, function coverage is100%, the condition coverage is95.1%,the linecoverage is98.7%, the FSM coverage is100%.This paper has discussed how to effectively combine function coverage and RAL(Register Abstraction Layer), assertions with the traditional method of validation.Combined with function coverage and RAL and assertions, the verification methodimprove the validation process of the observation, reduce the test cycle, ensure thecompleteness of the validation.