Research and implementation of BLMS digital calibration algorithm for pipelined ADC
|School||University of Electronic Science and Technology|
|Course||Communication and Information System|
|Keywords||Pipelined ADC BLMS digital calibration background adaptive calibration ASIC implementation|
As the semiconductor technology develops, the pipelined ADC design is toward all digital calibrating architecture, which can take great advantage of power consumption, error elimination, design complexity and chip area. In submicron, deep submicron and nanometer CMOS technology, the design complexity is moved to digital domain whenever possible, thus relaxing performance requirements and complexity of analog circuitry. Therefore, digital calibration has been extensively used in pipelined ADC and leads a boom in ADC development in recent years.Firstly, according to the structure of a pipelined ADC, the performance parameters are summarized. The nonideal of pipelined ADC is modeled, including comparator offset, sub-DAC error, overall offset, residue gain error and opamp nonlinearity. Then, based on the recent advanced researches home and abroad, the digital calibration techniques of pipelined ADC are summarized. Also, these calibration techniques are classified into5kinds:code domain equalization, split ADC, skip and fill, offline and PN injection.Each technique is analyzed from advantages and disadvantages.Secondly, this paper proposes a calibration alogrithm called blind least mean square (BLMS), which is an adaptive calibration worked on the background mode. This technique can calibrate both linear error and nonlinear error of pipelined ADC. Incorporated a200MS/s pipelined ADC, performance can achieve a SNDR of85.49dB, SFDR of95.21dB according to the simulation when input frequency of90.55MHz. Compared to the ADC without calibration, SNDR and SFDR are improved38.05dB and43.51dB, respectively.Finally, this digital calibration technique is implemented by full ASIC design flow, including RTL coding, synthesis, static timing analysis, formal verification, digital layout design and post simulation. This signal-mixed (analog+digital) ADC chip is implementd by IBM0.13μm CMOS technology, which die size is4.47*4.27mm2.