Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Memory > Magnetic memory drive > Disk memory

Improve and Optimize on PCI-e Data Synchronization of Dual Controller RAID System

Author YaoYuan
Tutor FengDan
School Huazhong University of Science and Technology
Course Computer technology
Keywords disk array dual controller data synchronization channel
CLC TP333.35
Type Master's thesis
Year 2012
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In the synchronous channel, we used to use the Dolphin’s DHX510PCI-e tosolve it.It can meet our requirement in the rate of transit. But there are also manyproblems on its own. PCI-e card transfer small pieces of data will less than theexpected data rate, even to a point that we difficult to accept it. Another problem isthat, Dolphin’s proposed design is targeted at multi-points (nodes>2) case, and ourdual-control server is obviously a point to point transmission mode, it will alwayswith only two nodes. Therefore, from the data structure and management proceduresit can both be simplified. Improve will begin in two point.One is to solve this problemabout small piece of data transfer. The other is to simplify the current PCI-etransmission level.In the transmission mode, the shared memory in SISCI layer is in charge of thetransmission directly by the CPU to store small pieces of data without performancedegradation. Improved after the transfer mode, the transmission will RDMA andshared memory. The end of the sender to send, use interrupts to notify the recipienthas already been sent, the liberation of the CPU to complete other work. Thebeginning and end of the transmission error detection module for error detection, erroris found, you can immediately terminate the program, send an error report. The entireinterface is the application above in SISCI layer, avoiding the cumbersomemanagement procedures supersocket layer to simplify the hierarchy of the PCI-eMake improvements to the PCI-e, the use of shared memory to solve the rate ofdecline in the transfer small pieces of data, while retaining the efficiency of theRDMA transfer large blocks of data transmission. Improved after the transmissionchannel on the one hand as the program’s interface, you can cache synchronizationmodule called directly. Cache synchronization module to synchronize, according tothe needs of users, select the appropriate data block size for transmission. On the otherhand, as an independent module, the successful completion, including error detectioninterrupt a series of tips and other features to ensure data integrity.

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