Research and FPGA Realization of Color Interpolation Algorithms in Digital Cameras
|School||University of Electronic Science and Technology|
|Keywords||color filter array demosaicing color interpolation algorithms FPGA|
Along with the wide usage of bayer color filter array (CFA) in digital cameras, theresearch and the hardware realization of bayer color interpolation algorithms havebecome a key technology. Meanwhile, the system requirements of miniaturization, highspeed, and intelligence have brought new challenges to the development of digitalcameras, and the rapid development of FPGA brought new ideas to meet these demands.Therefore, the main work, acquiring a color interpolation algorithm with high imagequality, high processing speed, and less resource consumption will be carried out andthen realized by FPGA. All work is listed as follows:To provide guidance for designing a new color interpolation algorithm, someclassical demosaicing algorithms have been reviewed and then deeply analysed from theimage quality, the resource consumption, and the real feature of processing. The newcolor interpolation meeting the requirements of high speed processing, less resourceconsumption, and high image quality in digital cameras has been designed combiningwith the smoothing characteristics of bilinear interpolation and the edge sensing natureof gradient interpolation algorithm; in order to give full play to the advantages of thetwo algorithms, the choice of the interpolation method is judged though the threshold,and the mechanism of gradient-based interpolation algorithm is used in the restorationof red component and blue component to ensure the three channels getting the sametreatment. After the fulfillment of algorithm design, the new algorithm has beenevaluated from the FPGA realization. Simulation test has been carried out throughMATLAB with some typical images, and the conclusion that the image quality of theimproved interpolation method get better can be gotten from the comparison of thesimulation results with different algorithms.The FPGA realization and testing programmes of the new interpolation algorithmhave been designed, and the scheme of data caching with less resource consumption andthe scheme of calculation with high real-time processing have been proposed. Then, theFPGA realization of interpolation algorithm with high real-time processing and lessresource consumption has been finished by VHDL with EP1C3T10017device of Altera Cyclone family. In the procedure of improving real-time processing, the ideas of parallelprocessing and pipeline processing have been adopted.The program design of hardware realization and the components selection of eachmodule have been finished. To provide meaningful guidance to the hardware design, thecaution items in the system design have been analyzed.