Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Computer network > General issues > Network equipment

Design-for-Testability Research and Optimization of TCAM-like Data Network Search Coprocessor

Author LiShaoJun
Tutor WangZiOu
School Suzhou University
Course Microelectronics and Solid State Electronics
Keywords DFT full-scan design fault location fault coverage ATPG
CLC TP393.05
Type Master's thesis
Year 2012
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In the face of increasingly complex network protocol packets, the network processor usually needs specified coprocessors to achieve a variety of functions.Among these coprocessors, the data network search coprocessor is the best choice for high-speed data search. Meanwhile, with the development of IC manufacturing technology and the improvement of design complexity, the issue of chip testing has been increasingly prominent. How to address the test problem properly at the beginning of design, which has become an important research direction for the field of integrated circuit design.On the basis of design for testability theory, this paper focuses on how to implement full-scan design for the TCAM-like data network search coprocessor, and then according to the test report, the logic defect is difficult to accurately locate. To solve this problem, and on basis of the theory of full-scan DFT, one novel approach, which could report the locations of logic faults in the standard cells, has been presented.The main contents include as follows:Weighing the pros and cons and considering the all kinds of factors, such as delay, place and routing, characteristics of the chip, the specific implementation plan for full-scan DFT is finally confirmed. Then we use the scheme in design for test of the chip and verify the correctness.Facing the challenge of positioning the logic defect, we solve the problem with a new scan method verified by simulation and successful tape-out by improving the circuit and the scan methodology.The samples’performance of the first tape-out meets the design requirements in all aspects. After adding some of the other functions and design for logical positioning scan, the chip is taped out secondly. The yield of the secondly418samples is85.6%, and4.5%in the remaining14.4%is successfully repaired with the defects information provided by the logical location scanning method, which is the best validation of effectiveness and practicality of this method.

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