Dissertation > Aviation, aerospace > Aerospace ( Astronauts ) > Space instrument,spacecraft devices,spacecraft guidance and control > Computing device > Data processing and recovery

Design of On-board Bus Networks Based on SpaceWire

Author ChenXiZhi
Tutor LiuXiaoFeng
School Harbin Institute of Technology
Course Information and Communication Engineering
Keywords SpaceWire standard bus network node interface router fault-tolerantarchitecture
CLC V446.9
Type Master's thesis
Year 2012
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With the advances in space technology and space applications, the function ofthe current satellite system showing the characteristics of diversity and complexityand the performance continues to increase, in addition to the request of thehigh-speed and high reliability of data transmission between the subsystems.Putforward higher requirements for the integrated transmission module reuse rate,lower development and manufacturing costs, improve compatibility. This feature isparticularly urgent demand on the small satellite platform, need a high-performancesatellite bus network and the corresponding diversification of structure to meet thelarge amounts of data, real-time control of data transmission, and demand forlow-cost reuse and fault-tolerant. SpaceWire technology is a high rate dataprocessing system model proposed in the next generation on-borad, point-to-point,full duplex, flexible, customizable fault-tolerant architecture serial bus network,based on the SpaceWire standard on-borad bus network characteristics, it isexpected to achieve the above requirements and data processing systems replace thetraditional star.In the paper, SpaceWire standard protocol of the detailed analysis of theSpaceWire routing network design requirements and in-depth study on the basis ofcompleted SpaceWire node interface router design and routing network architectureare finished. Including SpaceWire node interface and router hardware design andimplementation, functionality and performance testing, and SpaceWire routingnetwork architecture performance simulation analysis and testing. Altra’sFPGA-based platform, the design using Verilog HDL hardware description languageto achieve top-down, the various modules by function, respectively, to achievevalidation. Test results and analysis of the SpaceWire bus network designed to provethe rational design, transmission, real-time and fault-tolerant and stable performance,the basic functions and indicators meet the design requirements for the practicalapplication of the design of the bus network to provide the support of the theory andpractice.

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