The Development of a1200V Non-punch-through Igbt
|School||Beijing University of Technology|
|Course||Microelectronics and Solid State Electronics|
|Keywords||insulated gate bipolar transistor breakdown voltage threshold voltage latch-up phosphorus permeate segregation coefficient|
According to the given technical specification, the development of a1200VNPT-IGBT chip was completed. The chip structures combined of a FZ silicon singlecrystal substrate, non-punch-through withstand voltage layer, small size of P-well,planner gate and multi-steps ifeld plates or field irng with field plate etc.DESSIS and TSUPREM4were utilized separately simulate and verify thecharacteristic parameter and the technological process. The characteristic parameterincludes the breakdown voltage of multi-step ifeld plates or filed irng with field platetermination and the threshold voltage, saturation voltage drop and switchingcharacteristic of the cell structure. The technological processes included thermalgrowth of oxidation layer, ion implantation, junction propulsion and etch etc. Thefinal technological process and the slicing experiment confirmed in accordance withsimulated analysis.The samples succeeded at the first time, all the performance parameters met thegiven technical indicator and closed to the international products. The hightemperature reliability tests for168h were successful applied on the samples under thecondition of gate and reverse biased. The results achieved as follows:1.The breakdown voltage achieved more than1300V of the multi-step ifeldplates, which consisted of the gate oxide, ifled oxide, isolation oxide, andthick-layer of PSG, poly-silicon and aluminium electrode.2.The small size planner gate of square cell structure had free latch-up ability,including inner p+-well, double implanted NN+emitter, spacer, shallow trenchcathode contact etc. The optimization of threshold voltage is4.5V and thecollector leakage is less than lOOnA.The parameters required the designrequirements.3.The manufacture of back P type transparent collector was completed base onthe180|im thin chip. The saturation voltage is2.1V and the correspondingturn-off loss is4.4mJ. The trade-off data fit the expectant curve of simulation4.The reasonable process and technological parameter developed, which iscompatible with inland process platform.In addition, this work gives the contrastive analysis of simulation result andmeasured data. Some abnormal phenomenon in the development are also discussed, which including the simulation result of breakdown voltage of multi-step ifeld plate isless than the measured data, high temperature make the CE short duirng the pushP-well, the inappropirate segregation coefficient has influence duirng the P-Ringdiffusion etc.