Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design

Design of Single-loop Sigma-deltaadc Applied in Inertial Sensor

Author WangPengFei
Tutor LiuXiaoWei
School Harbin Institute of Technology
Course IC Engineering
Keywords Sigma-Delta ADC Single-loop accelerometer
CLC TN402
Type Master's thesis
Year 2012
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This dissertation introduced the working principle of the Sigma-Delta ADC, and then gave in-depth analysis of the structure of the Sigma-Delta modulator, designed the system architecture of single-loop the fourth-order with local feedback and feedforward summation modulator. The modulator system was simulated in Matlab. Based on the modulator system, design of the single-end modulator circuit was given. The module circuits of modulator are designed. Transistor-level circuit simulation is carried out in Cadence. Layout of the modulator was completed and post-simulation was employed. Sigma-Delta modulator chip was tested and the result was analyzed and discussed.In the system-level design, the dissertation used the full feedforward summation structure to reduce the outputs of the integrators. The system is easy to keep stable. Local feedback was used to optimize zeros. This increased the shaping ability to the modulator noise within the signal bandwidth. This dissertation adopted the single-loop fourth-order structure, over-sampling rate is256, the signal bandwidth is500Hz, and the sampling clock frequency is250KHz. The Simulink simulation shows that the SNR is145.6dB and the effective number of bits is23.89bits. Nonlinear model is given through the establishment of the quantizer. By the use of limit cycles, the stability of the modulator is analyzed. It is got when the quantizer gain k is greater than0.287the modulator is stable. If the input signal amplitude is greater than normalized amplitude-6dBFs, the modulator would be overload.In order to reduce the power consumption of modulator, the transistor-level circuit used the single-ended switched-capacitor circuit. Then it designed a general operational amplifier in the modulator. In order to reduce the noise of the first stage integrator, the chopper-stabilization techniques was employed. A dynamic comparator was designed to increase the speed with lower power consumption. And switched-capacitor circuits were used to achieve feedforward summation and local feedback. The overall circuit was simulated in Cadence by0.6um process. Transistor-level simulation result shows that the SNR is126.6dB, the effective number of bits is20.7bits. The single-end circuits produced harmonics by its nonlinearity. This dissertation completed the layout of modulator and the post-simulation shows that the SNR is123.7dB, and effective number of bits is20.26bit. Chip test result shows that the SNR is99.28dB and the effective number of bits is16.2bits.

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