A Fast-Locking Low-Jitter Pulsewidth Control Loop for High-Speed Pipelined ADC
|School||Xi'an University of Electronic Science and Technology|
|Course||Microelectronics and Solid State Electronics|
|Keywords||pipeline ADC pulsewidth control loop clock jitter charge pump CMOS|
Pipeline ADC has been adopted widely in high-speed and high-precision field with its advantages. However, with the increase of the effective bits and the frequency of input analog signal, the performance of clock jitter and duty cycle has a key influence on the static and dynamic performances in the ADC. Therefore the research of the circuit which can provide a clock signal with50%duty cycle and low jitter is getting more and more attentions from designers.Based on the existing research, this article proposes a new fast-locking, low-jitter and high-precision CMOS pulse width control loop based on the theory of delay locking loop. The proposed circuit achieves the modulation of duty cycle using the single edge of clock. This method guarantees the performance of ADC and lights the pressure of the clock signal source. For high precision, an improved charge pump with a follower circuit and self-biased loop was designed to decrease the voltage ripples for better accuracy and lower jitter. A start-up circuit was adopted to enable the PWCL lock rapidly.Using SMIC0.18μm3.3V CMOS process model, the simulation results show that within180ns the PWCL can lock the clock duty cycles for the accuracy of50±1%with10%～90%input duty cycle from50MHz to550MHz. The rms-jitter and peak to peak jitter is73fs and640fs at250MHz respectly. The simulations show this circuit has obvious advantages in locking-time, the range of duty cycle and precision, with comparison in the research work proposed by other designers. Now this pulse width control loop has been used in16bit105MHz pipeline ADC successfully.