Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits

FPGA Design and Implementation of Spacecraft EDAC System Based on TMS320VC33Development Platform

Author XuHaiBo
Tutor LiuHengZhu
School National University of Defense Science and Technology
Course Computer technology
Keywords Error Detecting and Correcting (EDAC) Single Event Upset(SEU) Digital Signal Processor (DSP) Field Programmable Gate Array(FPGA) Single-Error-Correcting Double-Errors-Detection (SEC-DED)
CLC TN791
Type Master's thesis
Year 2012
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Due to the impact of space radiation, there is larger probability of single eventupset occurrence in spacecraft memories, making a serious impact on the reliability ofaerospace equipment. In this thesis, based on the TMS320VC33and FPGAdevelopment platform, we have designed and implemented a32-bit EDAC system.When the SEU event occurs, the proposed EDAC system can be correct single bit errorand detect two bits error, which overcome the impact of the SEU to spacecraftcomputer.The main contributions of this thesis are listed as follows.1. The basic theory of the codec used for EDAC has been studied. We comparedthree single-error-correcting double-errors-detecting codes, including (39,32) extendHamming code,(39,32) Hsiao code and (40,32) SEC-DED code. Consideration of thelogic delay for FPGA implementation, we adopted the (40,32) SEC-DED code for our32-bit EDAC system.2. Based on the TMS320VC33development platform, we designed andimplementated the EDAC module using Verilog HDL. By sharing the subexpression,we optimized the the EDAC decoding logic and reduced the hardware overhead.Besides, the EDAC module can automatic write-back the correcting data to SRAMwhen1-bit error occurs. The FPGA synthesis results show that the maximumcombinational logic delay of the EDAC module in Actel FPGA A54SX72A is22.677ns.Board-level tests show that when the DSP operating frequency is60MHz, and DSPaccess the SRAM requires a wait of one clock cycle, the EDAC module can becompleted properly correct a single bit error and detect two bits error, which are meetthe application requirements.3. In order to hide the EDAC delay, we proposed a scheme to predict the SRAMaccessing address. When the work frequency of DSP is40MHz, the proposed EDACsystem based on memory access prefetch scheme works correctly. For the applicationwhich consists of large amount of sequential address access, the average memory accesstime of the EDAC system can be reduced.4. To ensure high reliability in the satellite EDAC system, the theory validation of(40,32) SEC-DED are completed, and the simulation test cases are also designed. Byestimating the simulation test time, we main focus on signle bit error and and theadjacent two bits error situations for the32-bit input data testing.

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