Dissertation
Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Arithmetic unit and the controller (CPU) > Arithmetic unit

The Design and Implementation of High-performance fixed-point Arithmetic Unit for SIMD DSP

Author LiGuoQiang
Tutor ChenShuMing
School National University of Defense Science and Technology
Course Software Engineering
Keywords YHFT-Matrix SIMD Adder Multiplier Arithmetic unit MAC
CLC TP332.2
Type Master's thesis
Year 2012
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In the application of image/video processing, radar signal processing and wirelesscommunication, as the data is large, high parallelism, high precision and real-time performance,mean while, these data have large mixed add and multiply operations, it is more and moreimportant for Digital Signal Processor (DSP) to process the parallelism data, which have largemixed add and multiply operations.In the background of “YHFT-Matrix DSP” research and design, this dissertationimplements a high-performance fixed-point arithmetic unit for SIMD DSP. This unit cancomplete all kinds of SIMD operations, such as addition, subtraction, multiplication,multiply-add, multiply-sub, dot product, complex operations and so on. The main works andcontributions are as follows:Based on Kogge-Stone Prefix adder, a SIMD adder using the methods of sign-bitcontrolling and carry-bit controlling is proposed. This adder can perform one32-bit, two16-bit,and four8-bit add/sub additions, all these operations can work in saturation mode andunsaturation mode.A new16-bit SIMD multiplier based on two16×8multiplier is proposed using the methodsof sign-bit preprocessing and stitching. The16×8multiplier is based on the Radix-4BoothEncoding and Wallace Tree, which is mainly constructed by5-2and4-2compressor, the finaladder is Kogge-Stone Prefix adder. This dissertation use four16-bits multipliers to implement a32-bits SIMD multiplier, which can perform one32-bits, two16-bits, two32×16bits and four8-bits sign/unsigned operations.Based on the instruction requirement analysis for the core algorithm of Mibench benchmark,LTE,4G wireless and H.264, a four-stage pipeline arithmetic unit is proposed to support allkinds of SIMD instructions. This dissertation also has completed the detail design of pipeline andinstruction set.The arithmetic unit designed by this dissertation has applied in YHFT-Matrix DSP. Thetaped-out testing shows that the proposed arithmetic unit can perform very well in theapplication-embedded SIMD DSP.

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