Design of A Multi-channel High-speed and Large Capacity Storage System
|School||University of North|
|Course||Measuring Technology and Instruments|
|Keywords||Multi-channel High-speed data Real-time storage High-Band-Buses operation pipeline operation|
With the continuous development of social technology, whether it is still in production andresearch and trials of life, the amount of data information generated has continued to increase.However, the transfer speed of data storage system, power consumption, reliability requirements areincreasingly stringent.At the same time based on different test requirements, test environment isdifferent, many in harsh environments to test one of the major tasks of data stored and difficult testnow. Based on the requirements of a specific test task, this paper design the data storage systems isused for completing the high-speed, large-capacity and multi-channel data acquisition inreal time and reliable storage.The issue of multi-channel high-speed data storage devices for recording an application during thetest serial LVDS, parallel LVDS, analog parameters such as signal, after the completion of dataanalysis and processing of these signals collection, storage, and the acquisition is complete, belongingcollection storage areas of study testing. On the basis of introduction of domestic and foreignhigh-speed mass data storage devices, the proposed overall design of the data storage system designedto complete large-capacity high-speed serial LVDS, LVDS parallel storage systems and analog data.After the design is modular in design, each channel data to the main control board, each channel in thereceiver substrate control commands and power control module that is independent of each module tocomplete its transmission and accurate real-time data storage tasks. FPGA design of each channel as aseparate logic control module, in the substrate transfer instructions, and start each channel receivesthe control module receives its data cache, which in turn determine the effective data, and writing datato the storage array. After testing the test, in the host computer command control, each channel dataread by the data returned under unloading channel decode analysis. The memory test equipmentusing the configuration structure that connected the independent channel card to thesubstrate, which can build to needed, maintain a simple, reusable strong according tothe specific task requirements.