Dissertation > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Data collection and processing systems

Design and implementation of high speed data acquisition system hardware of PCI based on Express bus

Author YangYang
Tutor SunLinLin
School Nanjing University of Technology and Engineering
Course Communication and Information System
Keywords Data Acquisition PCI Express GN4124 RocketIO Direct Memory Access
CLC TP274.2
Type Master's thesis
Year 2014
Downloads 28
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With the continuous development of computer science and VLSI technology, data acquisition system has enjoyed an extensive application, which places a higher requirement on bus transmission technology. Because of the synchronization demand of its own, parallel bus is limited in clock frequency. By contrast, with the self-timing function, serial bus doesn’t require the existence of a pulse clock, by that, serial bus can run up to a rather high rate. In the new generation of bus standard, PCI Express has a pure serial transmission architecture, supportting point to point transfer, and is expected to achieve the limit of copper wire transmission in linerate.In this thesis, we have researched the data quisition system based on PCI Express bus and its hardware realization. Except for introducing PCIe bus technology, a complete scheme of hardware design is provided, including the reception of high speed serial A/D converter, data buffer, realization of PCI Express bus, and we run the simulation based on the platform of Virtex V series FPGA. In the design alternative, we use RocketIO,which is provided by FPGA, to accomplish the reception of the high speed serial A/D, and adopt GN4124to realize the conversion between local bus and PCIe bus. In the specific realization, we give detailed introduction about data quisition part and bus part,and describe the function of each block, especially Direct Memory Access block in digital logic.This design is carried out by PCI Express×4lane. We can improve the performance of the bus if lane’s quantity can be expanded.

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