Dissertation
Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Computer applications > Information processing (information processing) > Pattern Recognition and devices

Design and Verification of the Embedded AVS Idct and Vld Hardware Module

Author WangXianKun
Tutor ChenXinHua
School Shandong University of Science and Technology
Course Computer System Architecture
Keywords Video codec AVS Inverse transform Variable length decoding Avalon bus SOPC
CLC TP391.4
Type Master's thesis
Year 2009
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With computers, microelectronics and communications technology continues to evolve , computers, multimedia and communications and other traditional industries gradually interwoven, integration. Audio , video and image transmission and exchange of information, etc. , has become the focus of people's communications , audio and video codec technology has become a modern research hotspot. AVS ( Audio Video Coding Standard ) is China with independent intellectual property rights of source coding standards, which are mainly used in standard definition video standard / high definition television . This paper reviews the development history of AVS and introduces its features, advantages , key technologies as well as the significance of China's information industry . In embedded systems , the system performance is affected by the constraints of microprocessor performance can not be achieved in soft real-time video decoding , it needs to carry out complex calculations hardware acceleration . Based on SOPC technology AVS decoder inverse transform and variable length decoding hardware design . AVS decoder inverse transform is the focus of this paper, reusable one-dimensional integer transform to the ultimate realization of two-dimensional integer transform , in the pipeline structure to maximize reuse calculation unit ; variable length decoding is widely used in a variety of video compression standard, this paper barrel shifter and accumulator combination to achieve a parallel stream decoding. HDL description language used to complete the design , simulation, integrated , through the Avalon bus module attached to the decoded under NIOS processor in SOPC Builder to build the test platform for authentication , and with the corresponding C language model results compare . After testing, the decoding module is operating normally , the correct results , indicators meet the requirements of real-time decoding .

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