Design and Implementation of FPGA Turbo Encoder/Decoder for LTE System
|School||Southwest Jiaotong University|
|Course||Communication and Information System|
|Keywords||Turbo codes LTE MAX-LOG-MAP decoding FPGA Block parallel Sliding window Interleave address calculation|
Turbo Code for its excellent performance, has been widely used in various types of wireless communication system , the LTE communication system, the channel coding scheme is one. However, due to the complexity of the iterative decoding , must be integrated into the relationship among complexity, latency and performance compromise , especially in the case of the information rate of up to hundreds of megabytes of high - speed Turbo codes is particularly important. In this paper, based on the algorithm of Turbo code performance analysis , focuses on the LTE communication system Turbo code encryption algorithm and FPGA implementation technologies . This paper first analyzes the LTE communication system Turbo codes algorithms and related technologies , and then positioning the problem on how to take advantage of the limited hardware resources to achieve high-speed encoding and decoding , and LTE latest protocol standards designed high - speed Turbo encoder . The thesis focuses on analysis of all kinds of advanced decoding algorithms , simulation, implementation and compare the performance of different algorithms . Then , based on the characteristics of the FPGA device with sliding window block parallel MAX-LOG-MAP decoding algorithm . Then according to the algorithm , the division of the functional modules , respectively, for the detailed design , and strict control of interface timing , in order to achieve the minimum decoding delay . In particular , the occurrence of interleave address using the real-time calculation methods , significant savings in logic and storage resources . Moreover , the input and output interfaces to meet the standard of Altera Corporation Avalon codec nuclear versatility , it can be easily applied to various types of products . The entire Turbo codec is the design using Altera Corporation 's QUARTUS Ⅱ development tools for system platform Verilog DHL code design with integrated on this platform , and functional simulation using Model Tech Company of Modelsim simulation tool , the last in Altera Stratix Ⅱ GX the FPGA chip verify the functionality and performance of the decoder .