Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design

DC Connected Block(dccb) Based Fast Circuit Partition Algorithm

Author ZhouXiaoWei
Tutor YangHuaZhong
School Tsinghua University
Course Electronic Science and Technology
Keywords SPICE Multi-core parallel computing Circuit Partitioning DCCB SCC VTM and DDM
CLC TN402
Type Master's thesis
Year 2009
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With the development of high-speed integrated circuit (Very Large Scale Integrated circuits, VLSI) circuit design scale growing and increasingly complex structure , sharp increase in the size of the system , the clock frequency and device density . This trend makes a series of auxiliary integrated circuit design simulation tools ( SPICE, Spectre , etc. ) face a severe test in the simulation cycle , simulation efficiency . In recent years, multi-core CPU , on the other hand , the rapid development and gradually occupy the CPU market led many core CPU also some foreign laboratory advent (MIT RAW 64 , Intel Polaris 80 ) . For circuit simulation software , to design a mature multi-core CPU hardware structure supporting circuit partitioning , task assignment and parallel iterative software algorithms to multicore parallel accelerated simulation of one of the key points of the subject . In this paper, starting from the circuit physical structure to absorb some of the existing VLSI circuit experience law on the basis of the graph theory , a module based on the DC path (DCCB) fast circuit partitioning algorithms for parallel SPICE circuit simulation . Process in accordance with the actual division of circuit algorithm , discussed in detail reads identification circuit network single establishment of the recording circuit components , with a division of the DC path the MOS transistor Group (DCCB) based on Tarjan recursive algorithm strongly connected component ( SCC ) identification, divided several important part of its application to SCC as the basic unit of streamlining Figure some optimization strategies . Machine time of the algorithm is mainly determined by the number of components in the circuit , but also by the DCCB and SCC circuit network number some impact . Using the DCCB for the base unit basic algorithm and the original algorithm on the actual test circuit machine time , dividing the solution quality and the speed of convergence of the parallel iterative series of comparisons , the experimental results to go along with the theoretical analysis and forecasting , is satisfaction. Compared with the traditional division algorithm for several classical our proposed algorithm itself increased the apparent speed ; Meanwhile, the system has good stability on the network the DCCB block and combining section , by the increase in circuit scale , structure very small change and the impact of changes in parameter settings . Over the past decade, the circuit is divided correlation algorithm has made great progress , and basically formed a theory and techniques

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