Research and Improvements of Multi-Core Processor Architecture for 40/100 Gbits/S Ethernet
|School||Beijing University of Posts and Telecommunications|
|Course||Computer Science and Technology|
|Keywords||40/100 Gbits/s Ethernet multi-core processor system architecture optimizations and improvements|
Research and improvements of multi-core processor architecture for Recently 40 Gbit/s transmission technology has entered the rapid and healthy development period of Generalized Deployment Phase. Meanwhile the 100 Gbit/s high-speed network related standards are gradually mature and will develop rapidly in the next 3-4 years. Recently, market survey shows that high-performance server market is not the same as previously expected by the sweeping impact of the global financial crisis. On the contrary, all major server vendors showed growth and market demand remained strong. Therefore, there is an urgent need for high-performance server with 40 Gbit/s or 100 Gbit/s of network data processing capabilities.As a key component of the server processing power, the network data processing capability of processor will determine the network data processing capability of whole system. A large number of experiments prove that single-core processor can’t deal with TCP/IP protocol stack efficiently under large network load, and parallel computing capability of multi-core processor becomes the new trend. So using parallel computing capability of multi-core processors is an important practical consideration of enhancing network data processing ability. However, the current network data processing ability of multi-core processor can’t meet the 40 Gbit/s Ethernet performance requirements. Therefore how to improve network data processing capability of multi-core processors becomes a hot issue.As pioneering research project, at first, this paper describes the current multi-core processors current status and development trend of upgrading network data processing capability, then introduces the Intel EDS execution-driven simulation system platform and its key technologies, and designed and implemented a complex model of multi-core processors based on EDS execution-driven simulation system platform, analysis the major bottlenecks of current multi-core processors during network data processing through quantitative analysis of experimental data, Elaborated the optimizations and improvements of multi-core processor architecture for the 40/100 Gbit/s Ethernet, mainly including three aspects of the improvements:multi-core processors architecture, operating system device drivers and network data processing. To verify and validate the optimization performance for multi-core processor architecture, this paper describes the comparison testing methods and testing cases before and after the improvement. Finally we could find that the processing capability of single-core processor after improvement is about twice of the pre-improvements. After improvement, the multi-core processors performance is no longer limited by comptition constraint among multi-core processors and the increase is nearly linear growth. After improvement, network data processing capability is nearly six times of before.This project is a joint project supported by Intel China Lab. They are in charge of design and debug Execute Driver Simulate system platform. And my responsibility of this project includes:modeling and analysis current multi-core processor bottleneck, design and implement the improvements of multi-core processor architecture for 40/100 Gbits/s Ethernet, test and validate the multi-core processor model after optimized. This project is presented in different of home and abroad meeting and recognized by most people.