Design of Crystal Oscillator with Low Power and High Stability
|School||Huazhong University of Science and Technology|
|Course||Microelectronics and Solid State Electronics|
|Keywords||Pierce crystal oscillator Low power High-stability CMOS technology|
Among many methods of getting frequency source, Quartz crystal oscillators are widely used to generate precision frequency standards. The resonant frequency of a crystal is accurately defined and its quality factor is high. Quartz crystal oscillators are used as clock sources in the synchronization and syntonization of distributed systems, precise definition of oscillation frequency and low power are the key points to make the quality of them. In this paper, we designed a low-power, high-stability Quartz crystal oscillators chip worked as clock based on 0.35μm CMOS process.The chip could work under two models: normal operating mode and power-dissipation model. In normal operating mode, it outputted a square wave signal; while in power-dissipation mode, it outputted high impedance state, many circuits were turned off, only a very small leakage current existed, which greatly reduced power consumption. For crystal oscillator frequency depending on supply voltage, therefore, a stabilizing circuit against supply voltage was designed to reduce the power noise and improve output signal stability; to improve the circuit ability with big load capacity, a high performance outputting buffer circuit was designed to amplify and shape the output signal; to meet the needs of different frequency signals, frequency dividing circuit was designed to output ?0, ?0 / 2, ?0 / 4, ?0 / 8 (?0 the crystal resonant frequency) four kinds of signals; nodes in the chip concerning high frequency signal were protected with circuit design, also while in layout design, the coupling between the high-frequency signal and high frequency components were accounted to make the greatest possible to reduce noise interference.Then the whole chip function simulation and typical performance characteristics simulation were presented. The thesis also introduced the full custom layout design of some key modules and the whole chip by using the tool of Virtuoso of Cadence. This chip has been taped out and tested. The results of test indicated that the power-dissipation has been reduced 60%, frequency stability raised ten times compared with the conventional structure.