Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Phase lock, the lock-in technique

Charge-Pump PLL Z-domain Analysis and Low Noise Design

Author LiFengBo
Tutor ZouZhiGe
School Huazhong University of Science and Technology
Course IC Engineering
Keywords Z - domain analysis Phase Noise The CPPLL low - noise design Output jitter
CLC TN911.8
Type Master's thesis
Year 2011
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?? ?? Recent decades, the phase-locked loop in the field of radio frequency (RF) communication and microprocessor widely used , especially with the integration of the continuous improvement , very large market demand for low noise PLL . However , the PLL and the large number of analog , digital , radio frequency circuit integrated will be the other circuits, especially the influence of the interference signals generated by the digital circuit , these interference signals are often transmitted through the way of the power supply, substrate, etc. , deterioration of phase-locked ring performance , which makes the low noise CPPLL entire system - on-chip design difficulties . This article through low-noise design for each module , and designed to eliminate the non - ideal effects of improved modules for low noise . This paper first introduces the working principle and application of the charge pump PLL , then the Z -domain analysis , compared with the previous structure derivation method is more simple , and this analysis in theoretical significance . Part in circuit simulation , in order to eliminate the phase frequency device ( PFD ) / irrational effect of the charge pump (CP) , the use of the effect of the added delay and latch unit PFD dead zone to eliminate the CP . The voltage - controlled oscillator (VCO) is designed primarily through the rational design of a bias circuit and a ring oscillator circuit to achieve the effect of a low - noise . In order to improve the speed reaches the working voltage of the VCO , the loop increases the starting circuit, thus improving the locking speed . Finally, we completed the layout , use of symmetry in the territory draw match, the protection ring design thinking to eliminate noise . In this paper, the design of the PFD reset pulse width of less than 4ns, you can basically eliminate the effect of the dead zone . CP branch current match good about each branch , and this structure can eliminate the clock feedthrough and charge injection shared effect . Design based on a low-noise VCO: center frequency of 216MHz, the lock-up time is less than 2 , the output frequency range of 120MHz, the working voltage of 1.0 ~~ 1.5V , the gain for the 240MHz / V , and phase noise is reduced to within the normal operating voltage range - 95.5 ~ -94dBc/Hz. Full imitation results show that the PLL lock output jitter is less than 30ps . The research content of this paper for phase-locked loop circuit Z - domain analysis and low noise design , providing a good guiding significance and reference value .

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