Key Technologies Research Based on the E1 Transmission Multiplexer Network Bridge Switchs
|Course||Electronics and Communication Engineering|
|Keywords||Ethernet Bridge FPGA PAUSE frame E1 CDR SDRAM Arbitration Lookup table|
With the growth of the Internet and communication services , significant changes in consumer demand structure , more and more business integration and personalization needs . As today's most widely used three networks : telecommunication networks , radio networks and the Internet , the integration between them is the trend . The Internet as of today's the most vitality the most widely used network , can be seen from the advance of all-IP networks in today 's society , the interconnection of telecommunications networks and the Internet is of great significance for network convergence . The E1 standard Ethernet as the foundation of China 's telecommunications network and the Internet network , the interconnection between them for the triple play of practical significance . The bridge is commonly used to achieve the connection between heterogeneous networks , and it works at the data link layer , after the simple processing of the data frame can be forwarded out, reduces the processing delay and complexity . In this paper, the E1 / Ethernet bridge as access equipment for telecommunications networks and Ethernet bidirectional transmission . In a variety of forms of the single- chip FPGA to implement the overall architecture of the system , has a short development cycle , low cost , and facilitate future upgrades and maintenance of the system . A wide range of E1 / Ethernet adapter , but basically all the multiple E1 bundled Ethernet bridge and the 1/4/8 the road E1 / Ethernet bridge products , 16 E1 / Ethernet bridge products not much , only a handful of domestic manufacturers to develop commercial products . Given 16 Road / Ethernet Bridge designed and implemented , and focus on the PAUSE frame flow control algorithm , bridge used in the implementation process of the E1 line clock recovery CDR, lookup table , SDRAM controller , arbitration polling algorithm and key technologies . All functions with verilog hardware description language to achieve , and concluded that the functional simulation system after the integrated gate-level circuit simulation and timing simulation , the basic right to verify that the system functions .