VLSI Research and Implementation for Motion Compensation Process in H.264 Decoding System
|Course||Circuits and Systems|
|Keywords||H.264 Motion compensation Sub-pixel interpolation Storage architecture Assembly line Reference image management|
H.264 is a new generation of video compression standard jointly developed by ISO and ITU-T [ 1 ] . It makes its compression performance than previous video compression standards have improved at least twice [2 ] by using a series of new features . However, efficient compression performance significantly increase the computational complexity , this presented a great challenge to the design of real-time hardware decoding system . H.264/AVC real-time decoding process , the motion compensation process about 80% of the whole decoding time . Sixth-order filter interpolation operation H.264/AVC support 1/4 pixel accuracy and up to 16 reference image , which caused the reference pixel positioning process and sub- pixel interpolation process to become a decoding system , the most complex and time-consuming two a link. Therefore, improving the efficiency of the motion compensation process is to improve the performance of the decoding system key . This paper studies the content and innovations include : 1 , This paper presents an efficient 4 - layer storage architecture , greatly reducing the amount of external memory access , to solve a large number of external memory access performance , power consumption . This paper presents a the two pipelined design method of the sub- pixel interpolation . First layer pipeline mechanism is based on the reference pixel reading and interpolation , the two water 4x4 divided block , and to achieve the parallel operation of a the different 4x4 block interpolation process . A second layer of water mechanism utilizes no dependence as well as horizontal and vertical interpolation operation process of symmetry, between the value of the 1/2 pixel interpolation operation algorithm to accelerate the operation process of each sub- pixel position of the pixel interpolation . 3 , the paper presents an efficient image management mechanism . Through the establishment of the direct mapping, of the reference image index (reference index, referred refidx) and the reference image index in the image buffer of an external decoder the (DPB index , referred dpbidx) as well as the optimization of the localization process in the direct prediction mode of the reference image , reducing complexity of the hardware and software of the motion compensation process for the realization of the two parts .