Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Digital circuits > Logic circuits

PCI-E interface -based data acquisition system FPGA Design and Implementation

Author TangAo
Tutor WuZuo
School Huazhong University of Science and Technology
Course Communication and Information System
Keywords Data acquisition card PCI Express bus Field Programmable Gate Array Gigabit Ethernet
CLC TN791
Type Master's thesis
Year 2011
Downloads 145
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With the information age, the rapid development of network technology, network to provide people with more and more informative. Meanwhile, with the growing size of the network, the network data traffic carried by rapid increase in high-speed networks to achieve real-time data streams, and efficient collection network monitoring and network security is an important issue. Data acquisition card system needs by the host server as carrier, in the real-time access to high-speed network data flow, high-speed processing is required after the high flow, high-speed data streaming to the host server. High Speed ​​IO bus technology enables development of this high-performance data acquisition systems become possible. PCI Express bus was developed on the basis of traditional bus the third generation of high-performance IO bus, with high-speed, high reliability, low cost and scalability, and other characteristics. Whether large servers or micro-computer system, both have good support for PCI Express. All the current required by the computer hardware to interact with the IO bus systems, PCI Express bus is a majority system of choice for high-speed transmission. In high-speed data acquisition system related technology research and study, based on in-depth understanding and analysis of the PCI Express bus architecture and implementation of the key technical points, combined with the system's functional requirements and want to achieve the performance requirements, this paper presents a kind based on the PCI Express bus speed data acquisition system design. The whole system including hardware logic design and software drivers in two parts, article from the logical aspects of the system hardware to elaborate system design and implementation. Hardware logic in the system development modular thinking, the whole system is divided into Gigabit Ethernet access, data filtering and matching the PCI Express bus DMA transfer three parts designed and implemented. By building the system software verification platform to test the functionality of the system and improve; in actual hardware test environment, with system software drivers for the system as a whole can do a full system testing and performance analysis. The system hardware logic to achieve a Xilinx Virtex-5 FPGA chip hardware support, to achieve a four-gigabit (4Gbps data stream) Ethernet data access, the data flow through the CAM chip matched filter, and the processed data block on the PCI Express bus is sent to the host server via DMA main memory. System provides for the DMA data transfer rate 3Gbps.

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