Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Wireless communications > Mobile Communications

FPGA-based 3G BERT Design and Research

Author GuanJian
Tutor LuoFengGuang
School Huazhong University of Science and Technology
Course Physical Electronics
Keywords BERT Field programmable gate array The third generation mobile communication network Serial Peripheral Interface Common Public Radio Interface
CLC TN929.5
Type Master's thesis
Year 2011
Downloads 32
Quotes 0
Download Dissertation

BERT the communication system is an important test instruments , often used in optical fiber communication and mobile communication network operations . These devices use a good BER maintain the network of technical support personnel quickly analyze network problems and has a vital role . This study based on FPGA technology, using a pseudo-random signal with the signal source to test 3G network base stations in the CPRI interface error rate , the rate of up to 6.144Gbps. Paper describes 3G BERT transmitter and receiver modules BER basic principles and design solutions for the communication required under interrupt signal source characteristics , the design of pseudo-random signal generator. While using FPGA to design CPRI protocol layer 1 physical layer , by detecting the CPRI layer 2 data link layer K28.5 signal synchronization signal , data synchronization and eleven comparison, the latter after a number of data errors encoded to 10 -bit wide data representation of data per 800 number of errors , the encoded data through the SPI interface is fed into AT89S51 microcontroller . For unique pseudo-random signal source , an analysis of its characteristics and the pattern of the circuit stream , and the use of the advantages of this pattern , at the same time for different network analysis methods of different error testing of the device . Text for each module includes a pseudo-random code generator , synchronous frame insertion and detection , 8b10b codec with string and conversion, data comparison module Verilog code for the simulation, while using protel software to complete the module and the microcontroller serial port minimum System . After the completion of all modules for BERT transmitter and receiver , respectively, of the simulation, the transmitter delay is about 10ms , 20ms or so at the receiving end delay .

Related Dissertations
More Dissertations