Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > General issues > Design

SystemVerilog-based functional verification module URAT

Author LiuHan
Tutor TangZuoAn
School Dalian University of Technology
Course Microelectronics and Solid State Electronics
Keywords UART module SystemVerilog VMM verification Formal Verification SVA
CLC TN402
Type Master's thesis
Year 2011
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