Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Frequency synthesizer technology,frequency synthesizer

Fractional-N frequency synthesizer Modeling and Design

Author YingWenRong
Tutor ZhouJianJun
School Shanghai Jiaotong University
Course Circuits and Systems
Keywords Frequency synthesizer PLL Fractional Charge Pump VCO
Type Master's thesis
Year 2011
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The frequency synthesizer is a wireless communication system, a core module , which gives the transceiver in the upconversion and downconversion circuitry provides the LO signal frequency is programmable . Therefore, the frequency synthesizer will directly affect the performance of the communication system communication quality. Currently, the PLL type frequency synthesizer is to achieve the frequency synthesizer of the most common architecture . Compared with the traditional integer frequency synthesizer , fractional-N frequency synthesizer for frequency accuracy breaking the loop bandwidth limitations , you can use higher input reference frequency, which makes the frequency synthesizer performance in many aspects have been significantly improved. Therefore , in recent years , fractional-N frequency synthesizer has been widely used. This type of phase-locked loop frequency synthesizer from the basic working principle , combined with Σ-Δ modulator works, systematic analysis and the establishment of a Σ-Δ fractional PLL linear model and phase noise model and discuss its generation mechanism and related spurious suppression techniques . Subsequently, this paper Σ-Δ fractional PLL phase noise performance , the model will be applied to the specific design of phase-locked loop , and gives in MathCAD software simulation results. End of this article elaborates PLL charge pump and voltage controlled oscillator these two key modules of the design principle and circuit implementation. Wherein the operational amplifier based on the charge pump circuit , a voltage controlled oscillator based on cross-coupled circuit configuration of the negative resistance . Both circuits are based on TSMC 0.18μm CMOS process for the design, implementation and simulation to achieve the expected performance requirements.

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