Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Phase lock, the lock-in technique

Design and realization of all-digital phase-locked loop circuit

Author LiuJunJie
Tutor LuoPing;LiWenChang
School University of Electronic Science and Technology
Course Software Engineering
Keywords Phase-locked loop DPLL The phase frequency discriminator IIR filter Numerically controlled oscillator
CLC TN911.8
Type Master's thesis
Year 2011
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PLL , as an important part of the modern clock circuit , has become an essential one of the modules in the VLSI , almost all of the digital integrated circuits are used in the phase locked clock generating circuit to provide on-chip high-speed clock . This article briefly describes the history of the development of the lock-in technology and its value in use and theoretical significance , and then based on the concept of phase-locked loop , composed of principle , a detailed description of the purpose and classification , given the typical digital phase-locked loop sub - module circuit and system structure , as well as the mathematical model of the digital phase-locked loop , the paper focuses the phase frequency discriminator , time-to-digital converter and digital -controlled oscillator three main modules , digital circuit design , design processes, as well as the design code specifications and skills . On this basis , the paper proposes several PLL sub-module circuit structure , including the phase frequency discriminator, the time-to-digital converter, a digital controlled oscillator and a new second - order IIR filter circuit , respectively, on their performance were analyzed. Details the digital back-end steps and note that the final design of phase-locked loop simulation testing , and related articles were compared . In this paper, the design of phase-locked loop using 0.13μm CMOS process to achieve top-down design methodology , completed all circuit design, simulation , and layout design , and by the layout extraction , after simulation and chip packaging and testing . Difficulty is digitally controlled oscillator (DCO) in the design and the design of digital IIR filters , due to the presence of parasitic parameters , process , voltage and temperature factors , the gain of DCO change , thereby affecting the stability of the entire loop Therefore , while improving DCO design , but also to design a stabilization circuit of the filter , so that in the case of the external conditions change , the PLL is still fast and stable functions . The design by mathematical modeling of the entire phase-locked loop loop , can rapidly and accurately identify the most suitable circuit filter .

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