Dissertation
Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > General issues > Design and Performance Analysis > Fault-tolerant technology

Study of Fault Tolerance Method Based on Redundancy Transmission for Network on Chip Soft Error

Author SongXiangMing
Tutor FuYuZhuo
School Shanghai Jiaotong University
Course Computer System Architecture
Keywords Network on Chip Fault-tolerant Reliability Triple Modular Redundancy
CLC TP302.8
Type Master's thesis
Year 2011
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With advances in semiconductor technology , the rapid development of this new technology and contribute to the network - on - chip (NoC) , also brings great challenges to the design of the NoC , mainly by the manufacturing process for the NoC system , the signal-to-noise and crosstalk , Electromagnetic the impact of factors such as interference , electron mobility increase , showing more frequently hard errors and soft errors . The system-level fault-tolerant and efficient method is a guarantee for the chip to work correctly . This paper presents a variety of methods based on the transmission of data redundancy , improve the reliability of the NoC communication . Taking into account the different error classification error cause lead to the network deadlocks and dead error strengthen the protection , use triple modular redundancy scheme ; protection to control information protection , consider the transmission of data , use a variety of redundancy schemes , design error injection model based on soft errors in the simulation platform simulation . The test results are displayed in the virtual channel buffer and link error injection (error rate is less than 0.002 ), the reliability of the transmission of the whole system reaches 99.99% or more , when the error rate is less than 0.0001 , the reliability of 99.999% or more . In this paper, the fault-tolerant program good protection network - on - chip data transmission reliability .

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