Dissertation
Dissertation > Industrial Technology > Automation technology,computer technology > Automation technology and equipment > Automation systems > Data processing, data processing system > Data collection and processing systems

The Design of a High-speed Data Acquisition/playback System Based on FPGA

Author LiYunFei
Tutor ZhouXiChen
School Nanjing University of Information Engineering
Course Signal and Information Processing
Keywords Data acquisition / playback PCI bus Digital Down Conversion IP core FPGA
CLC TP274.2
Type Master's thesis
Year 2009
Downloads 409
Quotes 1
Download Dissertation

The digital IF technology because of its stability, reliability , and flexibility become important modern radar receiver and signal processing technology , the technology is an important technology to improve the performance of modern radar , but also the inevitable trend of the development of radar receivers . Contrast phase auxiliary high-speed data acquisition system , regardless of its pre- simulation argument or its post - validation and algorithm improvements have a very important role . Therefore , the design of the radar system , there is an urgent need to design a high-speed radar data capture and playback systems , either as part of the digital radar receiver radar echo signal is collected in real time computer analysis ; computer in the radar echo signal playback to validate the need to test the signal processing board . According to the characteristics of a certain type of radar IF echo and combined with the results of previous studies , a radar IF signal high-speed data acquisition and playback system implementations , and on this basis to complete the design and testing of the system . The main function of this system is to achieve high-speed radar IF signal acquisition , high-speed transmission, storage , and high-speed playback . The implementation of the system discussed PCI controller - based burst transfer radar data to achieve high-speed data acquisition and playback . Radar IF echo signal acquisition, through ADC and digital down conversion in the FPGA will generate orthogonal two-way signal transmission to the computer , to achieve high-speed data acquisition ; When playback computer through the PCI DMA read in the data playback to the FPGA via RocketIO transfer between cards in order to achieve the hardware playback . The FPGA- IPcore achieve a PCI bus interface and signal processing and cache , which greatly improve the integration of the system , and enhance the reliability of the system . Finally, detailed design of the software part of the system , including the driver and application software design , the main driver for the application software provides a bridge hardware operation . Through the entire system for debugging and testing , the results prove that the system is able to achieve data flow velocity reaches 65MB / s high-speed data transmission of a radar signal .

Related Dissertations
More Dissertations