Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Microelectronics, integrated circuit (IC) > LSI,ultra LSI

Research on GALS Multi-Core Interconnection Based on A Delay-Insensitive Code

Author WangCan
Tutor JiangJianFei
School Shanghai Jiaotong University
Course Circuits and Systems
Keywords Multi-core GALS Asynchronous interconnection Delay-insensitive codes MP3 decoding
Type Master's thesis
Year 2011
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In recent years, with increasing number of modules in multi-core designs, it is more difficult to distribute a single synchronous clock to the entire chip. The complex clock tree also leads to high power consumption. In order to solve this problem, globally asynchronous locally synchronous (GALS) systems have been proposed, in which the entire design is divided into many independent clock domain.In this paper, a new asynchronous delay-insensitive link based on a 1-of-4 LETS code is proposed. The 1-of-4 LETS code has the coding efficiency, Transition power, throughput and hardware cost advantages. The new encoder and decoder are introduced and they are more robust since flip-flops are used instead of latches. Besides, the new approach is implemented by only standard cells.A new four-core GALS system is proposed based on the new asynchronous link. In this system, DSPs working in different clock domains are connected by the 1-of-4 LETS link and new interfaces are designed. The MP3 decoding program is analyzed carefully and memory spaces and running cycles are also given. Then it is divided into four parts and mapped to the GALS system.VCS, Design Compiler, Astro and Prime Power are used in the simulation and analysis. Performances of the 1-of-4 LETS link and the whole GALS system are presented.

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