Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Basic electronic circuits > Amplification technology,the amplifier > Amplifier

A Wideband Limiting Amplifier Design Basing on 0.18um CMOS RF Technology

Author WangWeiMing
Tutor GuoDongHui
School Xiamen University
Course Radio Physics
Keywords Limiting Amplifier Bandwidth Extension CMOS RFIC
CLC TN722
Type Master's thesis
Year 2009
Downloads 146
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These years, as the popularization of the internet, people require more information so the optical fiber is used in broadband client access gradually. As it determines some important parameters of the receiver, such as sensitivity and bandwidth, the limiting amplifier which affects the entire performance of network is a key device in the optical fiber receiver of optical fiber communication. Therefore, it is significant to design a high-performance monolithic limiting amplifier.In the thesis, a monolithic limiting amplifier chip with a mixed structure is designed based on the TSMC 0.18um CMOS RF technology. The mixed structure is composed of active feedback, capacity neutralization and frequency multiplier. It can effectively expand the bandwidth without increasing extra power consumption and layout area. Meanwhile, a signal loss detection module is integrated into the chip for low-power applications. The module can close or open output buffer to effectively reduce the static power consumption. In addition, a DC offset cancellation module is also integrated regarding to the mismatch caused by chip layout design and manufacture. It can significantly compensate the adverse effects of mismatch.The post-simulated results by Hspice indicate that the chip has a minimum 1mV input dynamic range, 50.4dB IF gain, and 5.2GHz -3dB bandwidth. It consumes only 71mW at static and 91mW at dynamic under 1.8V supply voltage. The proposed design can meet the application requirements of 4.25GBPS rate standard in optical fiber communication and downward compatibility other rate , such as 2.125GBPS, 1.0625GBPS rate. The die area of limiting amplifier including esd and padsis 0.6×0.4mm~2 , which properly realizes the requirements of research and development with high-performance and low-cost.

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