Dissertation
Dissertation > Industrial Technology > Radio electronics, telecommunications technology > Communicate > Communication theory > Signal processing > Digital signal processing

Block parallel DBF algorithm and its implementation

Author NiDingHua
Tutor ShengWeiXingï¼›MaXiaoFeng
School Nanjing University of Technology and Engineering
Course Communication and Information System
Keywords Digital beamforming SLCMV FPGA PowerPC
CLC TN911.72
Type Master's thesis
Year 2009
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With the development of signal processing techniques , adaptive digital beamforming technology has broad prospects for development in the military , civilian areas such as radar and communications . Adaptive digital beamforming technology radar adaptive capacity against active interference . This article block parallel digital beam forming algorithm hardware work mainly includes the following aspects: 1 ) the DBF large amount of arithmetic operations , as well as the characteristics of real-time high , and the characteristics of each combination of FPGA and PowerPC determine DBF FPGA PowerPC processor hardware implementations. 2 ) DBF algorithm using FPGA , limited accuracy ( data bits wide ) calculated from data must be used to the method of data interception . Structure SLCMV hardware implementation using MATLAB simulation , design a reasonable data interception program to ensure that the hardware structure is reasonable , correctness . 3) according to the characteristics of the operation of the different parts of the algorithm in the SLCMV SLCMV algorithm is divided into two parts to achieve. The large amount of calculation , the arithmetic portion of a lesser degree of complexity in the FPGA implemented using pipelining structure , including iterative process in which a large number of complex multiplications and complex accumulate operations ; smaller amount of calculation , the more complex part of the operator from PowerPC step calculation , constraints vector calculation . 4) by using the common input and output device ( GPIO ) , the RAM controller , RS232, and PowerPC405 build PowerPC hardware platform , designed reasonable control between the FPGA and PowerPC response mechanism, and to achieve the transmission of data between them , complete hardware commissioning and testing of the system . By comparing hardware output results with the results of the MATLAB program , confirming the correctness of the hardware implementation . 5 ) As a comparison, written entirely by the PowerPC serial the realization of SLCMV program , execute it and parallel programs , with an oscilloscope to test their running time . The tests show that the parallel programs running speed serial program 5138 .

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