The Synthesis Implementation and Verification of Bluetooth Chip
|School||Xi'an University of Electronic Science and Technology|
|Course||Microelectronics and Solid State Electronics|
|Keywords||Logic synthesis Scan chain Placement and routing Equivalence checking|
The increasing scale of the integrated circuit and the continuous progress of the integration process , put forward higher requirements on the design of integrated circuits . In deep sub-micron technology , and increased the proportion of the total delay due to interconnect delay connection spacing and supply voltage decreases , making the timing , signal integrity problems become major factors affect IC backend design . How to predict the true reflection of the deep submicron effects need a simple , repeatable , defined back-end design process . The paper analyzes the principles and logic synthesis combinational logic optimization and sequential logic optimization algorithm to use BlastCreate Bluetooth chip logic synthesis , setup time is not contrary to the phenomenon , combined with the structural characteristics of the chip developed to meet the design requirements of the Comprehensive constraints ; details the to adopt BlastFusion Bluetooth chip layout design process , including chip floorplanning and power / ground planning , layout , clock tree synthesis and routing steps such Bluetooth chip placement and routing strategies , determine the size of the chip is 8.4 square millimeter ; detailed study of the three chip back-end design verification technology , the Onespin 360 EC equivalence checking using PrimeTime static timing analysis and using the Calibre physical verification . The verification results show that to netlist correctly describe the function of the RTL code , setup time , hold time and transition time to meet the timing requirements , the physical connection relationship right , meet the requirements of the design rules .