Research and Design on Video Post-Processing System in AVS/H.264 Digital Video Decoding SOC Chip
|School||West China University|
|Course||Mechanical and Electronic Engineering|
|Keywords||Video decoding Video post-processing system SDRAM controller AVS/H.264 Graphics accelerator|
Digital TV, especially High-Definition digital TV, is a developing direction in television receiver system. The exiting 320 million analog TVs sets will be replaced by digital TV sets or need digital set-top boxes to receive the digital programs in China before year 2015. Digital video encoding and decoding chip, one of the basic components of digital-video devices, is still relying on import. In order to break the monopoly of foreign technology and promote the development of Chinese audio and video encoding decoding standard AVS(Audio Video coding Standard) with intellectual property rights,and be compatible with the most advanced video encoding decoding standard H.264. In this paper, we have done extensive research on design of video post-processing subsystem for AVS/H.264 digital video decoding chip SOC developed by Institute of Computing Technology of NingBo branch in Chinese Academy of Sciences.In this dissertation, we focus on the design of external data storage systems and I~2C bus controller on the basis of digital video post-processing system.In designing the digital video post-processing system, we post an algorithm which can achieve fine scalar image quality with lower hardware cost which has been used in the image-scaling module for H.264 and AVS video decoding chip; we design useful interface for TV users and realize man-machine screen display, which are called 2D graphics accelerator, it is easy for TV user to choose program listings, program information, channel selection, volume control, channel mode and so on and achieve good result.In designing the external data storage systems, the structure of the frame buffer is organized with macro-block as the unit because macro-block is adopted as the video decoding unit. Compared with the pixel-line storage structure mode, the proposed structure saves 87.1 percent SDRAM activation delay which makes full use of the memory bandwidth and improves the efficiency of memory access.In designing the I~2C bus controller, it sends different configuration info with unidirectional 125 bytes to the Adv7303a chip according to the standard of I~2C bus time sequence because of different display mode, and achieves Adv7303a chip’s function of digital to analog signal with lum and chroma signal.The designed video decoding SOC chip supports AVS video standard profile 6.0 level and H.264 main profile with the High-Definition resolution 1920 by 1080, 30 frames per second at maximum, and meets the need of real time of video images scaling and displaying in the post-processing system.