Development of PMC High-speed Data Transmission Board Design Based on FPGA-RocketIO_X
|School||Harbin Institute of Technology|
|Course||Information and Communication Engineering|
|Keywords||data transmission RocketIO_X PMC Allegro FPGA|
With the rapid growth of information technology, the need of data transmission has already overstepped the Mole Law (the performance of bus will double the original capacity every three year). At present the PC provides many kinds of high speed bus interface between the boards, in which the PCI bus finds favor in the Computer industry not only because of its open local bus specification but also the its outstanding performance in high-speed transmission. At the same time, the rising high speed serial interlink technique becomes the mainstream of development for its success on eliminating the clock and data dithering these years. A series of high speed serial standards come out continually, too. The full duplex Gb/s serial transceiver RocketIO_X with the function of CDR (Clock Data Resume) from Xilinx make it possible that actualizing these specifications in long distance and high-speed data transmissions for the designer.This thesis focuses on the high-speed data transmission between RocketIO_X and based on the PMC bus interface. This paper first makes a further treatment on the argumentation about the PMC interface project. Then, the article concluded some basic rules of the stack-up design. Subsequently, the article designs the PCB of the data data transmission board by using the PCB design software Cacence Allegro and simulates the critical nets topology of the PCB by applying the software SigXplore. Moreover, the article gaves a particular description of design process of the PCI interface based on FPGA (Field Programmable Gate Array), including the development of the driver; the article validates the PCI interface design at last.