Development of Pxibus High Performance Digital I/O Module
|School||Harbin Institute of Technology|
|Course||Instrument Science and Technology|
|Keywords||high performance digital I/O module PXIbus FPGA synchronous static random access memory (SRAM)|
A high performance digital I/O module based on PXIbus is studied and designed in this thesis, the high performance digital I/O module is an important instrument in data domain test. In the equipment debugging and fault diagnose of digital system, it can force digital stimulation on aim system and capture the response data of the system according to the actual demand, so it can provide valuable experimental evidence for the preference test and field debugging, fault diagnose of digital system. The high performance digital I/O module has comprehensive use and important applied value, the development and research of the digital stimulation and response module based on PXIbus is great importance to enhance the research level of data domain testing instrument in our country.On the basis of many technological reference,the whole scheme is discussed and analyzed in this thesis.Based on the scheme,the interface to the bus and the function part is designed. Aiming at the high demand of the technological performance such as large storage depth of each channel, high data rate and the amount of channels, the thesis refers to amounts of technological document and fully arguments technical performance, constitutes the collectivity scheme of which the core devices are three pieces of large capacitance, high speeding synchronous static random access memory (SRAM). The first one captures the response data, the second one outputs the stimulation data, the third one configures each channel to stimulation output/response input. In the way of three pieces of SRAM working in harmony and cooperating with continuous adderss sequence and synchronous clock, it outputs a sequence which stimulation and response can switch at any time. The thesis adopt FPGA to realize the function of control logic. The driver circuit is designed by bus buffer gate with 3-states outputs, ensure the stimulation output has enough driver current and the high-speed switch between stimulation and response. The variable frequency generated by dds enables the module to execute testing task at different data rate. In software design, the driver and soft panel of the instrument aredeveloped with LabWindows CVI. Aimmed at the actual use in test of digital system, realize the edit of logic level, timing relationship, input or output SRAM, the display and transfer to master computer of response data. A logic display window is offered to enable the user to analyze and observe the interesting segments in a complex data flow.The experimental results show that the technical performance has met all the design requirements.