Study of Signal Post-processing Method of Sigma-Delta Modulator for VoIP
|Course||Microelectronics and Solid State Electronics|
|Keywords||Sigma - Delta modulator Quantization noise Cascaded integrator comb filter Half-band filter Compensation filter|
Sigma-Delta analog-to-digital converter (ADC) is mainly composed by the Sigma-Delta modulator and filter, compared to traditional ADC, its main advantage is that does not require complex analog circuit structure, its cost may be declining, while the characteristics of the digitized so that can be integrated into other digital chips, therefore, Sigma-Delta ADC has been widely applied in the field of digital signal processing. Firstly, the input bandwidth of 20 KHz for VoIP chip 14 third-order Sigma-Delta modulator. Selection of the the 1-1-1 cascade structure design modulator, model in MATLAB modulator. Simulation integration, discussed and adjusted coefficient of each module to determine the output of the integrator is not overloaded. Processing the output of the third-order Sigma-Delta modulator levels. Derived through transform discrete signal Z domain, at all levels of the expression of the output quantization noise canceling circuit, merging the levels output behavior level simulation of the entire system. The results show that the signal-to-noise ratio greater than 86dB, and an accuracy of 14, basically meet the design requirements. Subsequently, the post-processing method on the the Sigma-Dleta modulator output signal. The structure of the the Sigma-Dleta modulator similar to the dual-slope ADC, including an integrator and a comparator, and a feedback loop of a digital-to-analog converter. This built-in digital-to-analog converter is just a switch, it will the integrator input switching to a positive or negative reference voltage. Sigma-Delta modulator to the high sampling frequency of sampling the input analog signal, and the difference between the two sampled low quantization, to thereby obtain the digital signal, and represented by a low bit digital Sigma-Delta code. The code is then sent to a digital decimation filter decimation filtering, high-resolution linear pulse code modulation digital signal. The decimation filter is actually equivalent to a pattern converter. The signal fed to the Sigma-Delta ADC after the quantification of very low resolution (1), but the sampling frequency is very high. After digital filtering process, such over-sampling is reduced to a relatively low sampling rate, while the resolution of the ADC is improved. Design a multi-level down-sampling filter to reduce the high-frequency signal output by the Sigma-Delta modulator. Analyzes a frequency characteristic of the cascaded integrator (CIC) filter, select the appropriate structure and order, to achieve a sampling frequency of the input signal decreased to 16 times, the attenuation of the quantization noise at a high frequency. With the half-band filter characteristics, as second-class down-sampling filter, respectively Kaiser window method and the best uniform approximation method to design half-band filter. Simulation filter designed by the two methods were selected after performance comparison of the best uniform approximation to design half-band filter. Further, taking into account the CIC within the passband frequency of the useful signal attenuation is relatively large, the design of a compensating filter for compensation processing, and the realization of the down-sampling two times. The results show that system-level simulation of the overall filter passband cut-off frequency of 20 KHz, passband ripple of 0.005dB, stop-band attenuation 93.4 dB down-sampling rate of 64, to meet the design requirements.