Research on IFF Mode S Burst DPSK Signal Demodulation Arithmetic and FPGA Implementation
|School||PLA Information Engineering University|
|Keywords||IFF Burst demodulation S mode Carrier recovery Clock Recovery FPGA Non- cooperative communication|
IFF Mode S burst DPSK signal contains a lot of state parameters of the aircraft, so the signal is intercepted and interpreted, can get a lot of valuable information. To obtain the information contained in the signal, the premise is to be detection and demodulation, good detection and demodulation algorithm to obtain information directly related to the completeness and correctness. This article relies on a particular airborne electronic signal receiving and processing system project, combining IFF Mode S burst DPSK signal characteristics, the signal demodulation algorithm for FPGA implementation and conducted a study to complete the main work and research results are as follows: (a ) according to the basic principles of energy detection algorithm, based on its appropriate improvements, we propose a burst IFF Mode S DPSK signal detection algorithms. The energy threshold of the algorithm is able to follow the channel change, a certain adaptive capacity, and which detects a bit error rate performance and detection than the original algorithm. (2) By S.BELLINI and others made the QPSK signal carrier frequency offset estimation algorithm for appropriate improvements, we propose a burst IFF Mode S DPSK signal carrier frequency offset estimation algorithm. The method is characterized by the angle changes using the signal amplitude by the signal itself instead of the carrier frequency offset estimate value, which is simpler than the original algorithm, and improves the performance of the estimated carrier phase. (3) choose to use Gardner timing error estimation algorithm and its improved on the basis of appropriate, propose a burst IFF Mode S DPSK signal clock recovery algorithms. The algorithm not only retains the original algorithm, but also reduce the timing loop jitter errors. (4) studied the IFF Mode S burst DPSK signal demodulation system architecture, through a variety of schemes are compared, choose to adopt FPGA DSP system architecture. Combined with extended functionality of the demodulation system design platform, the platform can be for a variety of pulsed electrical signals in real-time detection, demodulation processing, in order to adapt to a variety of small platform developed demodulation system provides a foundation. (5) studied the FPGA-based IFF Mode S DPSK signal burst carrier recovery algorithms and clock recovery algorithm for circuit design and optimization of some functional units, using VHDL hardware description language called IP core and its realization, based on demodulation system has been designed and a prototype system based on its verification of the algorithm, the results prove the correctness of the design and the design of processing speed, size and other aspects can meet system requirements.