Design and Implemetation of Concatenated System Based on CPM and LDPC
|School||Shanghai Jiaotong University|
|Course||Electronics and Communication Engineering|
|Keywords||Low Density Parity Check Continuous Phase Modulation Serially concatenated BCJR SISO Iterative Decoding FPGA|
Continuous phase modulation (CPM) can be decomposed into a continuous phase encoder (CPE) and a memoryless modulator (MM). The continuous phase encoder which is essentially a CPE convolutional encoder with a coding gain . Therefore, the phase modulation as the inner code , and a low density parity check LDPC code as an outer code , can form a concatenated code in the traditional sense system . Such a system to improve the effectiveness of the power is self-evident , the key is to control the complexity of the range that can be achieved . LDPC codes are very popular in recent years, an error correction coding. The use of information in the check node and variable node for transfer between the iterative decoding , has excellent performance and relatively low implementation complexity . This article describes the LDPC code encoding and decoding algorithms , H array design methods. Describes the CPM signal decomposition methods, the most commonly used Viterbi algorithm . Introduced CPM soft input soft output BCJR algorithm and proposed MSK cascade system with LDPC . Analysis of the cascade system performance, as well as interleaver impact on system performance , and proposed interleaver general design methods. Finally, a kind of LDPC codes codec FPGA implementation.