Hardware Design and Implementation of a the antiaircraft artillery fault detection system
|School||Nanjing University of Technology and Engineering|
|Course||Control Theory and Control Engineering|
|Keywords||Air defense artillery Fault detection PCI bus FPGA IRIG_B code|
With the development of anti-aircraft missiles , antiaircraft artillery, air defense weapons hegemony has been replaced , but in many cases, air defense artillery still has the incomparable advantage of anti-aircraft missiles . With the development of anti-aircraft artillery to automation , intelligent direction , its internal structure is also more and more sophisticated technology becomes more complex , the anti-aircraft artillery system fault detection also put forward higher requirements . This paper focuses on the hardware design and implementation of a the antiaircraft artillery fault detection system . In this paper, the design of anti-aircraft artillery fault detection system hardware is relying on a particular type of industrial control computer , based on the computer 's PCI bus to complete the acquisition and transmission of a certain type of anti-aircraft artillery system failure information . Hardware with a PCI bus interface board and external expansion of the one -way RS-232 interface , 2-way RS485 interface , 2 Road CAN interface , 1 channel IRIG_B code transceiver interface ; through the schematics and Verilog HDL language on Field Programmable Gate Array EP3C10E144C8N programming integrated timing board , address decoding , interrupt control GPS module seconds divider and board , , as well IRIG_B code codec functions . The PCI9052 chip external memory EEPROM configuration , board Plug and Play (PnP) functionality under Windows XP operating system . The board has passed the test of the data acquisition and communications . Test card transmission speed is fast , no delay , hardware , transmission error rate is small , plug-and-play function , able to work long hours under harsh environment to achieve a the antiaircraft artillery fault detection system design requirements.