Research on LON Node Using Dual Processors Based on Neuron Chip and Microcontroller
|School||Harbin University of Science and Technology|
|Course||Mechanical and Electronic Engineering|
|Keywords||LonWorks Neuron Chip SCM Input / output node|
LonWorks technology Echelon Corporation, USA in the early 1990s launched a completely open field bus technology, but only by virtue of a single processor Neuron chip is unable to complete a real-time multi-process, multi-task parallel processing, can not meet the acquisition amount and control the amount of field devices require more requirements of a LON node Neuron Chip MC143150 and microcontroller AT89S51 dual processor architecture-based development and design, to reduce the overhead of Neuron chip on the external events, give full play to it in Communication on the superiority of using AT89S51 field devices to exchange information quickly, to meet the requirements of real-time monitoring of the system. Technology development node theory exposition of the different levels, mainly related to the neuron chip and LonTalk protocol of LonWorks technology, the microcontroller technology hardware and software resources. This basis, focuses on a digital input / output control nodes and analog input / output control node hardware and software development process, covering the power supply modules, input / output channels, memory expansion, communication interface, neuron chip MC143150 the AT89S51 controller interface, clock, reset, crystal and other peripheral circuits, the Neuron Chip MC143150 the program design, microcontroller AT89S51 program design. Design process to fully consider the nodes to achieve the optimal performance of a variety of factors, the use of MAX1677, MAX8876 provide a stable power supply; AT29C512 external expansion 32KB of storage space; optical isolation, MAX197 and MAX527 as an input / output channel, not only accurate and rapid exchange of information, and also has a high anti-interference; FTT-10A free topology twisted pair transceiver as a system of communication interfaces to meet the high-performance, high common mode isolation requirements. A small volume, cost-effective, reliable operation node, MC143150 and AT89S51 controller interface to design a new serial bus SPI and I2C, it takes up less port for node PCB layout to save space, reduce chip hardware resources occupied, to adapt to the system integration, miniaturization requirements; MC143150 Neuron C language statement Neurowire and the I2C input / output objects with AT89S51 use of the C51 language simulation SPI and I2C bus interface for data exchange. Finally, the node performance optimization measures discussed. The experiments show that overcome the negative impact of the Neuron Chip event inspection scheduling mechanism, capable of complex system control, dual-processor architecture based on neuron chip MC143150 and the AT89S51 LON node.