Comparison of Fishbone and CTS clock tree

Advances in integrated circuit technology , improved integration , reduced size , physical design or physical design (physical design) has become increasingly complex. In order to let the physical design becomes more simple design method is commonly used in the clock ( clock ) and function ( function ) is divided into two separate parts . Clock timing circuit has different important position , clock tree (clock tree) that created the need to strive to improve the physical design of integrated circuits . The subject of this paper is to explore the high - performance LSI clock tree , fishbone network includes building a clock tree and clock tree synthesis , to discuss the difference between the different methods clock offset , as well as the impact on chip performance . First of all, of the integrated circuit in the status of the clock processing analysis . Secondly, in the concept of the basic concept of the clock tree , the classification and structure of the clock tree , the clock offset and forming reasons, the basic concept of the digital circuit timing made ??substantially elaborated after highlighting two nowadays applications in high - performance IC more clock design approach , the fishbone clock , and clock tree synthesis . Both clock application and the specific implementation method , respectively, both clock design method of chip . Finally , a module of the system clock structure with the fishbone clock and clock tree comprehensive analysis by clock skew , and the design of the degree of difficulty , the degree of resource - consuming , to compare the the fishbone clock and clock tree synthesis two the pros and cons of the ways . Mainly to the completion of the work are as follows : a: an overview of the status of the clock design of advanced high - performance LSI . b: to understand the basic concepts of the clock tree on the structure and classification of clock skew clock tree timing . c: fishbone clock and clock tree analysis comprehensive two clock design method to achieve , as well as the impact on chip performance . d: a high-performance large-scale design module to analyze the pros and cons of the two clock design methods fishbone clock and clock tree synthesis . Finally concluded .