Dissertation
Dissertation > Industrial Technology > Automation technology,computer technology > Computing technology,computer technology > Electronic digital computer (not a continuous role in computer ) > Emulator

A Research on Some Key Techniques in the Digital Channel Simulator

Author WuYaLing
Tutor ZhengLinHua
School National University of Defense Science and Technology
Course Information and Communication Engineering
Keywords Digital baseband channel Transmission impairments BER Shake Drift Digital channel simulator Multi-protocol serial interface BER generator
CLC TP337
Type Master's thesis
Year 2003
Downloads 194
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In this paper, based on analysis of the characteristics of the digital channel, combined with the current focus on digital channel direction proposed the idea to build a digital channel emulator platform. Topics involving more content, including: research familiar with the characteristics of the digital channel, familiar or achieve a variety of communication interface standards, the use of DSP technology, the use of LSI technology. Which it is necessary to take into account the complexity of the specific implementation, choose the appropriate means, methods, and pay attention to the versatility of the simulator, and can be modified according to the actual needs and upgrade, to achieve the required functionality. The paper specifically divided into the following parts: the first part is mainly theoretical research and analysis to study the characteristics of the digital channel, focusing on the error in the digital network transmission impairments, metrics such as jitter and wander, proposed a channel analog idea entirely different approach, namely, the main characteristics of the digital channel is mapped to the base bring analog. BER, jitter and wander in some of the important parameters and performance indicators. The second part is mainly based on the findings of the first part of the main factors affecting the digital transmission, such as bit error, jitter and drift simulation algorithm. Adjust according to current trends in the development of digital communications, some simulation performance, such as the BER simulation up to 10 -10 than the usual sense the on 10 of -6 < / sup> is much lower, so that makes digital channel simulator to simulate a wider range and higher precision. Principle analysis and specific implementation of two implementation methods, compared with the simulation method of the jitter and wander, select a relatively simple circuit implementation method, by using the value of the non-uniform sampling method, preferably on the dither signal analog, the generated sine wave is closer to the standard sine. The third part of the overall design of the digital channel simulator. The purpose of this part is to build a strong compatibility and scalability of the hardware platform, the basic digital channel path. In hardware design, the ultra-large-scale integrated chip DSP and CPLD, DSP selection take full account of its excellent computing power and a strong internal / external access function, while the use of in-system programmable CPLD jitter and drift, makes the system simple and flexible. Adhere to the principle of modular software design, not only in the functional realization look sharp and clear, but also conducive to future software upgrades. This through a combination of software, hardware, and software and hardware to achieve digital channel analog algorithm reflects the system's flexibility and versatility, but also facilitate the future expansion and upgrade. The fourth part focuses on digital channel simulator interface implementation, mainly to solve the serial interface circuit and UART implementation. Required for the system multiple protocols serial, the authors did not simply use multiple serial chip piled, but through careful research and selection, eventually SP507 multi-protocol serial chip as the system interface chip to support a variety of complex physical layer protocol of the interface circuit, the circuit design is more flexible, convenient and simple. G.703 interface circuit design and clever use of the selected DSP chip supports T1/E1 protocol characteristics, the the G.703 interface chip connected directly with DSP. The Design and Implementation of UART part of the National Defense Science and Technology University Graduate School Dissertation is another characteristic of the system design. Through CPLD chapter UART design, on the one hand, to fill the currently used UART chip shortcomings, such as low-rate, too complex functions, on the other hand can reach some of the special requirements of the system, such as the format of choice, thereby enhancing the The utilization of the entire system, while reducing the expenditure of resources. Keywords: digital baseband channel transmission impairments error the jitter drift digital channel simulator multi-protocol serial interface error generator

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